1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly this invention relates to the planarizing, by chemical-mechanical polishing, of metal-filled trenches of integrated circuit structures.
2. Description of the Related Art
Aluminum and tungsten metals have long been used in integrated circuit structures as filler materials for vias and contact openings as well as for the construction of metal lines or interconnects. However, with ever increasing demands for faster speeds, there has been renewed interest in the use of copper as a filler material for vias and contact openings instead of tungsten, as well as for use in metal lines instead of aluminum because of the well know low resistance of copper, compared to either aluminum or tungsten.
But there are negative aspects to the choice of copper for via filling or in the formation of metal lines. The usual patterning of a blanket-deposited metal layer through a mask to form a pattern of metal lines or interconnects cannot easily be carried out using copper, resulting in the need to first deposit a dielectric layer such as silicon oxide, and then form a series of trenches in the dielectric layer corresponding to the desired pattern of metal lines or interconnects. The trench surfaces are then lined with a barrier layer or liner (to prevent migration of copper into the dielectric material, as well as to promote adhesion of the filler metal to the trench surfaces), and then filled with copper metal by respective blanket depositions. Finally, the surface portions of both the barrier layer and the copper layer, formed over the top surface of the dielectric layer during the blanket depositions, are removed using a planarization process such as a chemical-mechanical polishing (CMP), leaving the desired pattern of metal lines or interconnects in the trenches, with the copper metal in the trenches separated from the silicon oxide sidewalls of the trench by the barrier layer.
While the copper lines or interconnects formed using such procedures provide the desired increased speed of the conductor, and the presence of the barrier layer between the copper and the silicon oxide dielectric material addresses the problem of diffusion of the copper ions or atoms into the silicon oxide sidewalls, the removal of the surface portions of both the barrier layer and the copper layer by chemical-mechanical polishing (CMP) can result in erosion of the surface portion of the copper remaining in the trench, due to the non-homogeneous removal of the barrier layer and the copper by the CMP process once the surface of the barrier layer is reached and exposed during the CMP process.
Turning now to prior art FIGS. 1-3, the formation of copper interconnects or lines in a dielectric layer of an integrated circuit structure, in accordance with the prior art, will be illustrated, using the so-called single damascene process, it being understood that the same planarizing problems are also present when using the dual damascene process. As shown in FIG. 1, a first silicon oxide dielectric layer 20 may be formed over an integrated circuit structure 10 which may comprise active devices previously formed in an underlying silicon substrate and filled vias or contact openings previously formed in an underlying dielectric layer. Such vias or contact openings provide connection, for example, with underlying gate electrodes and source/drain regions of MOS devices of integrated circuit structure 10 formed in the silicon substrate, as is well known to those skilled in the art.
Still referring to FIG. 1, formed in silicon oxide dielectric layer 20, are trenches 22 and 24. Trenches 22 and 24 may be formed in dielectric layer 20, for example, by etching dielectric layer 20 through a resist mask, to divide dielectric layer 20 into the illustrated pattern of trenches in dielectric layer 20. Trenches 22 and 24 represent or illustrate a series of trenches generally formed in dielectric layer 20 in a pattern corresponding to a desired array of metal lines to electrically interconnect, for example, underlying filled vias or contact openings (and the devices connected thereto) with other portions of the integrated circuit structure.
Over trenches 22 and 24 and the illustrated upper surfaces of dielectric layer 20, is formed an electrically conductive highly conformal barrier layer 30 comprising, for example, tantalum metal, tantalum nitride, tungsten metal, tungsten nitride, titanium metal, or titanium nitride, or combinations of same. Barrier layer 30 is blanket deposited over the surfaces of trenches 22 and 24, and the upper surface of dielectric layer 20, by a suitable deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or any other suitable deposition process to a thickness of, for example, from about 100 xc3x85 to about 1000 xc3x85.
Following the formation of barrier layer 30, a layer of copper metal 40 is blanket deposited over the structure by any suitable deposition process to completely fill the remaining portions of trenches 22 and 24, as well as depositing over the portions of barrier layer 30 previously deposited on the top surfaces of silicon oxide dielectric layer 20, as also shown in FIG. 1.
Following the blanket deposition of copper layer 40, the structure is subject to a chemical-mechanical polishing (CMP) process to remove all of the copper on the portions of barrier layer 30 on the top surfaces of dielectric layer 20, as shown in prior art FIG. 2, leaving only copper portions 42 and 44 in respective trenches 22 and 24. After removal of all such copper from the top surfaces of layer 20, the CMP process is continued to remove all underlying portions of barrier layer 30 over the top surfaces of dielectric layer 20, leaving only a liner of barrier material on the walls of the trenches separating the copper metal in trenches 22 and 24 from the silicon oxide surfaces or walls of the trenches, as shown in prior art FIG. 3.
The initial CMP planarization, resulting in the structure shown in prior art FIG. 2, basically comprises the uniform removal of the upper portions of previously deposited copper layer 40, and this portion of the CMP process proceeds until the upper surface of barrier layer 30 is encountered, i.e., exposed. However, to then remove the portions of barrier layer 30 lying over the upper surface of oxide layer 20 requires further polishing and it has been found that such further polishing results in removal of the upper surface of the copper in trenches 22 and 24 at a faster rate than the removal of the portions of barrier layer 30 lying over the top surface of dielectric layer 20. The result, as shown in prior art FIG. 3, is erosion of the exposed surface of the copper, leaving a dished or concave upper surface of the copper filler material in trenches 22 and 24, as shown, respectively, at 52 and 54 in trenches 22 and 24. Furthermore, while the problem of surface erosion of the metal trench filler material during CMP planarization has been discussed and illustrated with respect to its occurrence with copper, the problem also exists when tungsten is used instead of copper, which includes, for example, in vias or contact openings where tungsten is used more often as the filler material.
It would, therefore, be desirable if the process for forming a pattern of metal interconnects or lines in previously formed trenches and/or vias in a layer of insulation material could be carried out without erosion of the metal surface of the filler metal in the trenches.
An improved process is provided for forming an integrated circuit structure wherein trenches are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a filler layer of a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive materials from the upper surface of the dielectric layer, wherein the improvements comprise:
a) before the planarizing step, forming over the filler layer of second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the barrier layer comprising the first electrically conductive material; and
b) then planarizing the structure to remove:
i) the planarizable material;
ii) the second electrically conductive material; and
iii) the first electrically conductive material;
above the upper surface of the dielectric material;
whereby the planarizable material above the second electrically conductive material in the trenches protects the second electrically conductive material while the first electrically conductive material is being removed from the upper surface of the dielectric layer by the planarizing step to prevent erosion of the upper surface of the second electrically conductive layer.